In data processing systems, peripheral interface units are used to connect low-speed peripheral devices to a higher speed system bus used by central processing units (CPUs), direct memory access (DMA) devices and other types of bus masters. The peripheral interface unit serves to isolate these lower speed devices and avoids additional bus loading on the higher speed system bus. A typical access time to access a peripheral device may be on the order of 4–10 system bus clocks once an access request has been received by the peripheral interface unit. These accesses degrade system performance due to the long access latency. System performance therefore may be improved by buffering data for the peripheral write accesses. An example of a write buffer in a peripheral controller is discussed in U.S. Pat. No. 5,712,991 by Wichman et al. entitled “Buffer Memory for I/O Writes Programmable Selective”. The Wichman et al. controller dedicates a buffer for each peripheral device in a computer system and stores information in each buffer based upon instruction type.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.